1. Field of the Invention
This invention relates in general to electrostatic discharge (ESD) and more specifically to ESD circuitry arrangement in an integrated circuit.
2. Description of the Related Art
An integrated circuit may be subjected to a damaging Electrostatic Discharge (ESD) event in the manufacturing process, during assembly and testing, or in the ultimate system application. In conventional integrated circuit (IC) ESD protection schemes, special clamp circuits are often used to shunt ESD current between the power supply rails and thereby protect internal elements from damage. A type of ESD clamp circuit, known as an active Metal Oxide Semiconductor Field Effect Transistor (MOSFET) clamp circuit, typically comprises two parts: a trigger circuit and a large MOSFET clamp transistor. The conduction of the clamp transistor is controlled by the trigger circuit. Active MOSFET clamp circuits may be employed in networks distributed along the power buses to provide robust and consistent ESD protection for all the Input/Output (I/O) pads in the IC. Multiple embodiments of such networks are shown in U.S. Pat. No. 6,385,021 entitled “Electrostatic Discharge (ESD) Protection Circuit” and in U.S. Pat. No. 6,724,603 entitled “Electrostatic Discharge Protection and Method of Operation.” Both patents are assigned to the assignee hereof.
FIG. 1 illustrates one such distributed ESD network 100 in an IC to protect multiple I/O pads in a bank of I/O cells. Five I/O cells 110-114 are shown in FIG. 1. However, the distributed network may encompass a larger bank of I/O cells around the IC periphery region as indicated by the dots placed to the left and right of the elements shown in FIG. 1. I/O cell 110 includes an external connection (I/O) pad 120 which is coupled between a VSS bus 102 and a VDD bus 103 via diodes 122 and 123, respectively. A clamp N-channel MOSFET (NMOSFET) 125 is connected between the VSS bus and the VDD bus. The gate of clamp NMOSFET 125 is connected to a trigger bus 109. Not shown in I/O cell 110, but assumed present is circuitry for normal (i.e. not ESD) I/O cell operation. I/O cells 111-114 are each identical to I/O cell 110. I/O cells are cells that include circuitry for conveying input signals, output signals, or both input signals and output signals.
In addition to I/O cells, the I/O ring around the periphery of an IC typically contains several power (VDD) and ground (VSS) cells. An example VDD cell 116 and VSS cell 117 are shown in FIG. 1. The VDD cell includes an external connection VDD pad 130 which connects to the on-chip VDD bus 103 while the VSS cell includes an external connection VSS pad 132 which connects to the on-chip VSS bus 102. The VDD cell contains a trigger circuit 135 which is powered by the VDD bus and the VSS bus and provides an output signal which drives trigger bus 109. The VDD cell also contains a clamp NMOSFET 136. The gate (a control terminal of a MOSFET) of clamp NMOSFET 136 is connected to the trigger bus. The VSS cell contains trigger circuit 140 and clamp NMOSFET 141, which are similar to the trigger circuit and clamp device in the VDD cell.
Integrated circuits are often most susceptible to damage during positive ESD events coupled onto an I/O pad referenced to grounded VSS. The response of ESD network 100 to this event applied to I/O pad 120 in FIG. 1 is as follows. Diode 123 forward biases as the I/O pad voltage very quickly ramps above about 0.8V. This produces a rapid voltage increase over time (dV/dt or voltage slew rate) on the VDD bus 103. Trigger circuits 135 and 140 may be of a type of trigger circuit that contains a resistor-capacitor (RC) based voltage slew rate sensor tuned to respond only to very fast ESD-related transients, and a series of inverting buffer stages to drive the trigger circuit output. In response to an ESD dV/dt transient on the VDD bus, trigger circuits 135 and 140 drive trigger bus 109 to the VDD bus voltage. This turns on the multiple clamp NMOSFETs 125, 136, and 141 distributed in the I/O and power/ground cells, respectively. Once turned on, this cumulative network of clamp NMOSFETs acts as a low resistance shunt between the VDD bus and the VSS bus. The clamp NMOSFETs remain conductive for a period of time which is determined by an RC time constant of the trigger circuit. The trigger circuit should drive the clamp NMOSFETs for a period of time which exceeds the typical duration of an ESD event (e.g. 300-600 nanoseconds), yet avoid false triggering of the clamp NMOSFETs during normal ramp up of the VDD bus. With some examples, the VDD ramp-up during normal operation typically requires 1-5 microseconds.
In some IC designs, there are very few or no power or ground pads cells placed in the I/O ring. This is a problem with the ESD network approach of FIG. 1 because trigger circuits must typically be placed at least once for every 10-15 I/O cells in order to efficiently drive the clamp NMOSFETs distributed in the nearby I/O cells. For example, it would be difficult to ESD protect an unbroken, tightly abutted bank of 20 or more I/O cells placed without any intervening power or ground cells. In addition, advanced packaging options often eliminate power or ground cells in the I/O ring altogether. For example, in an IC designed for flip-chip packaging, off-chip connections to the power and ground buses are typically made directly down onto buses in the IC core region, without the need for any periphery power or ground cells in a bank of I/O cells. Thus there is a need for a new ESD network approach especially which can fully protect a large bank of tightly abutted I/O cells without any intervening power or ground cells.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted. The figures are not necessarily drawn to scale.